STM32F101R8 is running at 36MHz off its internal clock. One of its three general purpose timers, TIM4, aims to generate four different time based interrupts.
These should be proper internal time base design, without any hardware signals are involved - neither as inputs or outputs.
The design is to use the 36MHz as the driving clock, divide it by the TIM4_PSC = 0x00FF and get a 7.11 uSec timer clock.
Then, by using TIM4's four CCRx registers - getting the 4 required delays from the time that TIM4 started its run.
I must be missing something, either within the TIM4 understanding or within its programming, as the fired interrupts' delay is completely different than expected.
Also, CCxIF bits within SR register never indicated which of the 4 events had occurred, actually SR=00 so it's not really clear what triggers TIM4's interrupt.
TIM4 registers are configuration after reset:
TIM4->PSC = 0x00FF;
TIM4->CCR1 = 0xBBBB;
TIM4->CCR2 = 0xCCCC;
TIM4->CCR3 = 0xDDDD;
TIM4->CCR4 = 0xEEEE;
TIM4->EGR = 0x001E;
TIM4->DIER = 0x001F;
TIM4->CCER = 0x0000;
TIM4->CR1 = 0x0288;
TIM4->CR1 |= 0x0001;
Any support here?