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SPI clock phase setting

Question asked by p.ben on Jan 6, 2015
Latest reply on Jan 7, 2015 by Clive One
I am using STM32L152 part to talk to a digital accelerometer using SPI.
The SPI signal timing diagram for the accelerometer is illustrated in the attached figure.

Looking at the diagram, it is clear that the spi clock polarity should be high (1).
I'd like some help determining the spi clock phase.

The data output by the L1 device is latched by the accelerometer in the second (rising) edge. So to honor the required setup time, I am thinking that the L1 device should send SPI data out at the first (falling) edge.
But I am wondering if this would mess up the timing for SDI sampling, because bit D7 is not ready by the falling edge of clock for the eighth bit (immediately following A0).

Any clarification is appreciated.