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DAC Internal Reference Settling Time

Question asked by yellin.david on Jan 4, 2015
We are building a digital LED buck converter with slope compensation as described AN4885 High brightness LED dimming using the STM32F334 Discovery kit.

The discovery kit application uses the DAC to generate a 250 kHz internal reference ramp signal with amplitude approximately 250 mV, by use of the DMA. 

It appears that the designers took into account a DAC settling time of approximately 900 ns when designing the firmware. ("In order to compensate the DAC output settling time, the top of the curve is synchronized with the CMP4 event instead of the PER event.") The datasheet for the MCU specifies a DAC settling time of 3 to 4 uS when used for generating an external voltage.

In the case of our application we plan to amplify the current sense signal to a maximum of 3 V in order to use the full 12 bit resolution of the DAC. However we don't know what effect this will have on the internal settling time, if any. 

According to AN4566 Extending the DAC performance of STM32 microcontrollers, it is possible to reduce the DAC settling time by use of an external op-amp, for a maximum of 4.5 msps. It appears from this application note that the internal settling time must be much lower than the value in the datasheet (so approximately 220 ns). 


- Is it possible to use the DAC for generating a 250 kHz internal ramp at 3v peak-to-peak at all?
- If not, would it make sense to use an external amplifier to compensate the DAC signal and feed it back into the comparator inverting input?
- If it is possible to generate such a signal internally, what delays should be taken into account?