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STM32F429 NAND FLASH & SDRAM

Question asked by zhou.weiqiu on Dec 16, 2014
Latest reply on May 26, 2015 by marini.ivan
We constructed a board using STM32F429. We use SDRAM for memory of LCD and NAND flash for program data. SDRAM and NAND flash share FMC bus of MCU. We have 2 problems at present:
1. When we access NAND flash, there is disturbance on LCD display. Once operation on NAND flash stops, LCD restores to normal.
2. We define heap in SDRAM. When we move data from NAND flash to the heap, data is corrupted in heap. If we move heap data first to MCU internal SRAM, and then move it from internal SRAM to SDRAM, there is no problem.
It seems there is conflict NAND flash and SDRAM when both of them accessing the FMC bus. Our question is, dose STM32F429 support NAND and SDRAM for LCD display simultaneously? If yes, how to get rid of disturbance on LCD while accessing NAND flash or external SRAM? 
If someone had such experience, could you please give us some guidance?
Thanks!
Joe

//Following are codes of NAND flash initialization and driver.
p.FMC_SetupTime = 0x4; 
p.FMC_WaitSetupTime = 0x4;
p.FMC_HoldSetupTime = 0x6;
p.FMC_HiZSetupTime = 0x2;

FMC_NANDInitStructure.FMC_Bank = FMC_Bank2_NAND;
FMC_NANDInitStructure.FMC_Waitfeature = FMC_Waitfeature_Enable;//FMC_Waitfeature_Disable;//
FMC_NANDInitStructure.FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_8b;
FMC_NANDInitStructure.FMC_ECC = FMC_ECC_Disable;
FMC_NANDInitStructure.FMC_ECCPageSize = FMC_ECCPageSize_512Bytes;
FMC_NANDInitStructure.FMC_TCLRSetupTime = 0x00;
FMC_NANDInitStructure.FMC_TARSetupTime = 0x00;
FMC_NANDInitStructure.FMC_CommonSpaceTimingStruct = &p;
FMC_NANDInitStructure.FMC_AttributeSpaceTimingStruct = &p;

FMC_NANDInit(&FMC_NANDInitStructure);

/*!< FSMC NAND Bank Cmd Test */
FMC_NANDCmd(FMC_Bank2_NAND, ENABLE);
////////////////////////////////////////////////////////////////////////////////////////////////////////////
int Nand_ReadPageWithSpare2048(int PageNum,uint8_t *const DataBuf, uint8_t *const Spare)
{
volatile uint8_t *pCLE;
volatile uint8_t *pALE;
volatile uint8_t *pDATA;
volatile uint8_t nand_buf;
uint32_t i, curColumm, curRow;
volatile uint8_t j;
char srambuf[NANDFLASH_PAGE_FSIZE];   //栈里的缓存

i = 0;

pCLE = K9F1G_CLE;
pALE = K9F1G_ALE;
pDATA = K9F1G_DATA;

curColumm = 0;
curRow = PageNum;

*pCLE = K9FXX_READ_1;

*pALE = (uint8_t)(curColumm & 0x000000FF); /* column address low */

*pALE = (uint8_t)((curColumm & 0x00000F00) >> 8); /* column address high */

*pALE = (uint8_t)(curRow & 0x000000FF); /* row address low */

*pALE = (uint8_t)((curRow & 0x0000FF00) >> 8);


*pCLE = K9FXX_READ_2;


i=20;
while(i--) ;

if(DataBuf != NULL)
{
for(i=0;i<NANDFLASH_RW_PAGE_SIZE;i++)
{
srambuf[i] =*pDATA;
}
}
else
{
for(i=0;i<NANDFLASH_RW_PAGE_SIZE;i++)
{
j=*pDATA;
}
}
if(Spare!=NULL)
{
for(i=0;i<NANDFLASH_SPARE_SIZE;i++)
{
srambuf[NANDFLASH_RW_PAGE_SIZE+i]=*pDATA;
}
}
else
{
for(i=0;i<NANDFLASH_SPARE_SIZE;i++)
{
j=*pDATA;
}
}

if(DataBuf != NULL)
{
for ( i = 0; i < NANDFLASH_RW_PAGE_SIZE; i++ )
{
DataBuf[i] = srambuf[i];
}
}
if(Spare != NULL)
{
for ( i = 0; i < NANDFLASH_SPARE_SIZE; i++ )
{
Spare[i] = srambuf[i+NANDFLASH_RW_PAGE_SIZE] ;
}
}


return 1;
}

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