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SPI - CS timing

Question asked by Gerber on Oct 23, 2014
Hi,

to send SPI data I use the code below:

GPIOE->BSRRH |= GPIO_Pin_13;   
received_val=SPI2_send(0x16);                                           
GPIOE->BSRRL |= GPIO_Pin_13;

The problem is the CS (GPIO_Pin_13) already becomes high at the rising edge of the last CLK pulse. I have implemented several checks (code below) to make sure the data has been send before raising the CS signal again.

while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
SPI_I2S_SendData(SPI2, data / 256);
// be sure that the character goes to the shift register
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
SPI_I2S_SendData(SPI2, data);
// be sure that the character goes to the shift register
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
// and then be sure it has been sent over the wire
while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET);

Whats the best solution in order prevent the CS level already going high at the rising edge of the last CLK pulse?

Thanks.

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