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STM32F051K8 dies on setting PLLON

Question asked by wohlland.per on Sep 30, 2014
Latest reply on Oct 1, 2014 by waclawek.jan
Dear community,

I am having an issue with the setup of the PLL, which causes the CPU to jump into reset. Used libraries are libopencm3, toolchain is the latest arm-none-eabi release for linux (4.8 2014q3), JLink used as debug interface. I also tried older compiler- and gdb-versions and used different boards to evaluate, every time with the same result.

The code in question is the following:


// Ensure PLL is disabled
RCC_CR &= (~RCC_CR_PLLON);
 
// Wait for PLLRDY bit to be cleared
while ((RCC_CR & RCC_CR_PLLRDY) != 0);
 
// Make flash adjustments
FLASH_ACR |= FLASH_ACR_PRFTBE;
FLASH_ACR = (FLASH_ACR_LATENCY_1WS | (FLASH_ACR & (~(0x07))));
 
// Select HSI as PLL source
RCC_CFGR &= (~RCC_CFGR_PLLSRC);
 
RCC_CFGR = (RCC_CFGR_PLLMUL_MUL12 | (RCC_CFGR & (~(0xf << 18)))); //RCC_CFGR_PLLMUL)));
 
// Set APB and AHB prescaler to 1, which effectively is no prescaling
RCC_CFGR = (RCC_CFGR_PPRE_NODIV | (RCC_CFGR & (~RCC_CFGR_PPRE)));
RCC_CFGR = (RCC_CFGR_HPRE_NODIV | (RCC_CFGR & (~RCC_CFGR_HPRE)));
 
// Enable PLL ...  dies right here
RCC_CR |= RCC_CR_PLLON;
 
// Wait for PLL to become ready
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
 
// Select PLL as system clock
RCC_CFGR = (RCC_CFGR_SW_PLL | (RCC_CFGR & (~RCC_CFGR_SW)));
 
// Wait until the hardware has set PLL as system clock
while ((RCC_CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);

When debugging, the registers seem to have to values I intend them to have. But when executing
RCC_CR |= RCC_CR_PLLON;
, the cpu jumps into reset. Tried pretty much everything imaginable. Addresses of registers seem fine, too.

Hope you guys can give me some help!

Best regards, Per

EDIT: If someone could lend me his hands with the code formatting, that would be marvelous! Thanks, Clive!

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