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STM32L0 RCC_CFGR read-only?

Question asked by Carsten Schumann on Sep 30, 2014
Latest reply on Sep 30, 2014 by Carsten Schumann
Hi,

I'm using an STM32L051 microcontroller for a low power application. Actually I am working on a state change between low power and normal operating mode. Therefore I am trying to switch the system clock to PLL but it seems the RCC_CFGR register is read-only for some unknown reasons. I am using the HAL library and the following initialization sequence (directly copied from the examples):

  RCC_ClkInitTypeDef RCC_ClkInitStruct;
  RCC_OscInitTypeDef RCC_OscInitStruct;

  /* Enable Power Control clock */
  __PWR_CLK_ENABLE();

  /* The voltage scaling allows optimizing the power consumption when the device is
     clocked below the maximum system frequency, to update the voltage scaling value
     regarding system frequency refer to product datasheet.  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

  /* Enable HSI Oscillator and activate PLL with HSI as source */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
  RCC_OscInitStruct.HSICalibrationValue = 0x10;
  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
    ErrorHandler();

  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
     clocks dividers */
  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
    ErrorHandler();

After this sequence the RCC_CFGR:SW bits are switched to HSE (0b11), RCC_CFGR:SWS is HSI (0b01) and RCC_CFGR:PLLSRC is switched to HSE allthough HSE is deactivated and NO external clock source is available. Manual writing to the CFGR register does not change the value.

NOTE: There was no other initialization prior to this sequence.
1. Any ideas what's going wrong?
2. Under which conditions are the RCC registers locked (except the backup domain stuff)?

Thanks in advance,
Carsten Schumann



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