AnsweredAssumed Answered

STM32F407 Half bit error on SPI3 MISO on multi SPI solution

Question asked by kay.dee on Sep 22, 2014
Latest reply on Sep 25, 2014 by kay.dee
Hi all!

I am running a 3 MCU solution were all MCU:s are communicating 21MHz full duplex SPI to eachother. As:

MCU1 SPI3 Master <-> MCU2 SPI3 Slave
MCU1 SPI2 Master <-> MCU3 SPI2 Slave
MCU2 SPI2 Master <-> MCU3 SPI1 Slave.

The SPI data transfers are with DMA and most of the time it works very well. Communication between MCU1 <-> MCU2 and MCU1 <-> MCU3 starts almost at the same time, and MCU2 <-> MCU3 starts when half the MCU1 <-> MCU2 traffic is finished (half buffer interrupt) and the data between MCU2 <-> MCU3 is approx. half the size so all traffic will end approx. at the same time. The traffic cycle repeats every 5 ms.

But at random occations, a peak pulse about half a bittime (or half CLK period) is emerging on the SPI3 MISO on the MCU1 <-> MCU2 SPI. This pulse is in phase with the CLK signal on the MCU1 <-> MCU3 SPI. The amplitude is the same as a normal signal. It's like the CLK signal from SPI2 is fed out on SPI3 MISO pin for a very short time but I cannot see that PC11 signals or PB13 can be cross connected somehow.

The upper signal in the attached photo is the SPI3 MISO signal, and the lower wave is the SPI2 CLK signal. The error peak is second from the end in the upper wave. It differs compared to the other pulses in the upper wave. The last pulse in the upper wave is the last bits of SPI3 MISO transaction. The SPI2 (CLK signal on lower wave) ends a couple of bytes later...

How is this possible? The similarities between the error pulse in the upper MISO wave and the lower CLK wave, when it comes to amplitude and phase, are so big that I almost can exclude other disturbance sources on the board.

Do anyone know any sensitive parts in code to take into notice, as when clearing ISR flags or something?

Kind regards



Attachments

Outcomes