I am using timer1 channel 1 as output compare, to generate a pulse of variable period.
Desire output – In the beginning the output remain low for 4 ms(delay period) and then pulses of variable periods as 5.8, 3.6, 2.7,2.3, …. The desired time periods are stored in RAM. (Frequency range 170 Hz to 1.5 KHz)
The timer clock is configured to 1 MHz frequency. The output mode is set to toggle mode and the polarity is set to active high. The capture compare interrupt is enabled.
And the capture compare register is set to delay period and then in next interrupt, the capture compare register set to first period and next period will be updated after the one pulse is completed.
The problem facing is that the beginning delay period is variable and sometimes missing.
If initial delay is not missing then the following output periods are correct as expected. If the low period is missing then the first period start from low rather than high which results in wrong steps
I is the correct expected output, II is wrong one.
why timer output compare not working properly ?? why it miss the first delay ??