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SDADC Limitations Explained

Question asked by wired on Aug 8, 2014
Latest reply on Aug 8, 2014 by wired
After reading through the promotional material, datasheet and reference manual for the STM32F3's SDADC and spending a few days trying to obtain a 16KHz sampling rate, I believe some clarification of the limitations of this peripheral are in order.  For the record, these limitations should be explicitly stated in the overview of this peripheral. Until that happens, I hope this can be an informative source of information that will save others from the frustration I experienced in trying to store a single channel at 16ksps to a DMA buffer (which BTW it turns out is impossible with this device).

My reading of ST's literature led me to believe I could easily acquire samples to DMA at 16 ksps for a single channel. Here's the real story:

1) Timer-controlled conversions are limited to ~12.4 ksps, regardless of the number of channels. You CANNOT sample a single channel faster than this using a sample rate of choice.

2) A sample rate of ~16.67 ksps per second can be obtained for a single channel in CONTINUOUS MODE ONLY, when operating with the maximum SDADC_CLK of 6 MHz in normal mode. If this is the rate you want, rejoice... you hit the jackpot.

3) A sample rate of 50 ksps per second can be obtained  for a single channel in CONTINUOUS MODE ONLY, when operating with the maximum SDADC_CLK of 6 MHz in fast mode. If this is the rate you want, rejoice... you won the lottery.

4) Sampling rates between 12.4 ksps and 50 ksps can only be controlled by SDADC_CLK, which can only be set to specific divisions of the system clock, leaving very limited sample rate options. Sample rate can only be set by changing your system clock rate and/or the SDADC clock divider.

In continuous mode, sampling occurs every 360 SDADC_CLK cycles in normal mode, and every 120 SDADC_CLK cycles in fast mode (after the first measurement, which still takes 360 cycles).

I have not delved into the DMA capabilities in continuous mode, so I can't comment on whether it is possible to have these conversions go directly to a DMA buffer. What I can definitively state is that if you want to do timed conversions (using a timer) and store to DMA, you will be limited to ~12.4 ksps for a single channel.

If someone out there has been able to accomplish this, do tell.  It would be welcome news to myself and revealing to ST support.

Good luck with your SDADC applications!

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