AnsweredAssumed Answered

STM32F401RE SPI Init without CMSIS Functions

Question asked by christopher H on Jul 22, 2014
Latest reply on Aug 5, 2014 by gonzalez.laurent

Hello,
I have a problem with the initialization of the SPI1 from my STM32F401. It doesn't work and I don't now what I doing wrong or what I forged. When I write something in the data Register ( SPI1->DR), nothing happens. The System Clock comes from per PLL from a HSE CLOCK.  I hope someone can say me what I doing wrong.
Sorry for my bad English.

void init_spi_disp(void){
// ENABLEN DES GPIO FPR ALTERNATING FUNKTION
//RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
#if 1
 
RCC->AHB1ENR |= RCC_AHB1ENR_CRCEN;
RCC->APB2ENR  |= RCC_APB2ENR_SPI1EN; // ENABLE SPI 1FUNKTION CLOCK
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | // PORT A ENABLE
                RCC_AHB1ENR_GPIOBEN;  // PORT B ENABLE
GPIOB->MODER |= GPIO_MODER_MODER4_0|  // CS LCD as output
                GPIO_MODER_MODER5_0;   // CS SD as output
GPIOB->MODER &= ~( GPIO_MODER_MODER4_1 |
                  GPIO_MODER_MODER5_1 );
GPIOB->MODER |= GPIO_MODER_MODER10_0; // SET PB10 (DC) as Output
GPIOB->MODER &= ~GPIO_MODER_MODER10_1;
// SET OUTPUT SPEED AS FAST
GPIOA->OSPEEDR |= Bit10 | Bit11 |
                  Bit12 | Bit13 |
                  Bit14 | Bit15 ;
 
 
 
GPIOA->MODER |= GPIO_MODER_MODER5_1| // SET PA5 PA6 PA7
                GPIO_MODER_MODER6_1 | // AS ALTERNATING FUNKTION
                GPIO_MODER_MODER7_1;
GPIOA->MODER &= ~(GPIO_MODER_MODER5_0|
                  GPIO_MODER_MODER6_0|
                  GPIO_MODER_MODER7_0);
 
GPIOA->AFR[0] |= Bit20 | Bit22 |  // SET ALTERNATING FUNKTION  TO SPI1..4 (AF5)
                 Bit24 | Bit26 |
                 Bit28 | Bit30 ;
GPIOA->AFR[0] &= ~(Bit21 | Bit23|
                   Bit25 | Bit27 |
                   Bit29 | Bit31  );
// SET Default
SPI1->CR1 = 0;
SPI1->CRCPR =  7 ;
SPI1->CR1 &= ~( SPI_CR1_SPE); // DISABLE SPI
// Disable SPI for Register SET
SPI1->CR1 &= ~ (SPI_CR1_BIDIMODE) ; // SET SPI AS 2-line unidirectional mode
SPI1->CR1 &= ~ (SPI_CR1_CRCEN) ;  // DISABLE CRC CALCULATION
SPI1->CR1 &= ~ ( SPI_CR1_DFF) ; // SET DATA FRAME TO 8 BIT DATA FRAME
SPI1->CR1 &= ~ ( SPI_CR1_RXONLY); // SET FULL DUPLEX
SPI1->CR1 |=   SPI_CR1_SSM; // MUSS ICH DAS SETZEN ICH BIN DOCH MASTER ?????
 
#if 1 // DIV /4
SPI1->CR1 |= SPI_CR1_BR_0; // SPI DIVISION /4 for 21 MHZ Frequenc
SPI1->CR1 &= SPI_CR1_BR_1 |
            SPI_CR1_BR_2 ;
#else // DIF 128
SPI1->CR1 |= SPI_CR1_BR_2|
            SPI_CR1_BR_1;
SPI1->CR1 &= ~(SPI_CR1_BR_0);
#endif
 
/**FRAM FORMAT NOCH BETRACHTEN */
//SPI1->CR1 |= SPI_CR1_LSBFIRST ; // SET LSB TRAMSMISSION FIRST
 
SPI1->CR1 |= SPI_CR1_MSTR; // SPI is Master
SPI1->CR1 &= ~(SPI_CR1_CPOL|
               SPI_CR1_CPHA);
 
 
SPI1->I2SCFGR &= ~(SPI_I2SCFGR_I2SMOD);
 
// INTERRUPTS NOT ENABLED
SPI1->CR1 |= (SPI_CR1_SPE); // ENABLE SPI1
 
 
#endif
 
}

Outcomes