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SPI master slave sync problem

Question asked by khalo.hilwane on Jun 12, 2014
Hello,

I'm trying to use stm32F3 as SPI slave, and communicate with master via another board.
I've configure SPI1 as slave. Slave clock set to 18MHz.
I'm using NSS hardware, and getting ETXI once CS gets low in NSS pin.

The Slave board has its clock configured to 10MHz.
CPOL and CPHA are compatible in master and slave.

I'm trying to transfer 40 bits, with 8 bit of address.
the master transmit 5 bytes in the same CS.

I'm viewing all my signals with scope(CS, Clock, MOSI, MISO):
when the CS is low:
- The master transmit the correct signals 0x0A for the address and(0x01, 0x02,0x03,0x04)for data.
- The slave receives the correct data and send its proper data (0xAE, 0x47, 0x05,0x41).
The problem is that the master receives incorrect data in the MISO.
The data in MISO line is: 

1. 0x05(when the MOSI value=0x0A(the address), then 0x41, 0xAE, 0x47, 0x47

I trying to understand where is the problem, in the master or in the slave?
Thanks for any help

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