AnsweredAssumed Answered

SWD layout

Question asked by mackinnon.calum on Jun 12, 2014
Latest reply on Aug 10, 2014 by jj.sprague

Does ST have any layout recommendations for using their Serial Wire Debug capability?  We are planning on using the Cortex M ETM debugging functionality.  This includes using the TRC CLK, TRC DATA[0], TRC DATA[1], TRC DATA[2], TRC DATA[3] and TRC DATA[4] signals.  I understand that these can be high speed and may need special layout considerations.

Thanks for your help!