The DMA for stm32F4 series has some advanced functions, could I ask for clarification here?
Concurrent stream: Can two streams transmit data at the same time? Since one byte transfer is allowed. If the bus width is 32bit, 4 concurrent transmission is possible. Btw, what is the width of the AHB bus for STM32?
FIFO mode: If concurrent transmission is not possible, I guess FIFO could be used here. FIFO would help to wait data ready from low speed peripherals to DMA without occupying the AHB bus. When a certain amount of data are ready, the chunk of data will be sent to memory together. Is my understanding correct?
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream
What does that mean? How many data can be stored in the FIFO? 4 or 4*32?
Double-buffer type transactions: double buffer transfers using two
memory pointers for the memory (while the DMA is reading/writing
from/to a buffer, the application can write/read to/from the other
buffer). -----From reference manual of STM32F4
My question is: During the DMA transmission, the AHB bus is not available for Cortex M4, how could the application read from the other buffer?