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STM32F207 FSMC Bus Turnaround timing

Question asked by peelo.frank on May 29, 2014
Latest reply on May 29, 2014 by waclawek.jan
I need some help in understanding the Bus Turnaround time of the FSMC. I think I have it right, but don't want to burn out the data bus in finding out I'm wrong. Could someone who knows, confirm please?

My STM32F207 has a slow device and a fast SRAM connected to the address and data buses. They are accessed with the basic SRAM Mode 1 shown in section 31.5.4 of RM0033 using NE1 and NE2 respectively.
  • According to "Table 174. FSMC_BTRx bit fields" in the Mode 1 description, BUSTURN controls "Time between NEx high to NEx low (BUSTURN HCLK)"
The description of the BUSTURN field in FSMC_BTR1..4 says:
(BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if EXTMOD = ‘0’
(It does say BUSTRUN. I didn't mistype that.)

So is the time between NEx high to NEx low BUSTURN HCLK or (BUSTURN+1) HCLK?

I think it has to be (BUSTURN+1) HCLK, otherwise I don't see hwo NEx would ever go high if BUSTURN was 0. In other words, NEx will always go high for one HCLK, and BUSTURN extends this. Is this correct?

  • In all the timing diagrams, the data bus is driven for a short time after NEx goes high. For the external devices on the bus, this time is in the datasheet. If the FSMC is driving the bus, I cannot find the time value (tEHEL min, presumably). Would it be within 1 HCLK?
  • I am 99% sure that if I do a read on NE1 with BUSTURN=8, and then a read on NE2, that there will be 9 HCLK between NE1 going high and NE2 going low. In other words, when RM0033 says "Time between NEx high to NEx low", the two NEx don't have to be the same line. Is this correct? 
If not, is it possible to have devices of different speeds attached, and not run them all at the speed of the slowest?

Many thanks