AnsweredAssumed Answered

SPI master slave sync problem

Question asked by rogel.zohar on May 29, 2014
Latest reply on Sep 9, 2014 by Montassar BEN ROMDHANE

I'm trying to use stm32l152 as SPI slave, and communicate with master via PC with 
USB-SPI device.

I've configure SPI2 as slave. Slave clock set to 4MHz.
I'm using NSS hardware, and getting ETXI once CS gets low in NSS pin.

The PC program using USB-SPI device.
The clock is configure to 3MHz.
CPOL and CPHA are compatible in master and slave.

I'm trying to transfer 24 bits, with 8 bit buffer of STM32.
the master transmit 3 bytes in the same CS.

I'm testing all my signals with scope:
The master transmit the correct signals (0x78, 0x55, 0x33).
The slave code receive the correct data and send the proper data (0x12, 0x34, 0x56).
The problem is that the master receives incorrect data in the MISO.
The data in MISO line is: 

1. 0x12, 0x12, 0x34
2. 0x56, 0x12, 0x34
3. 0x56, 0x12, 0x34 

The first byte is sent twice, and as a result all data is shifted.
I trying to understand where is the problem, in the master or in the slave?
Thanks for any help