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STM32F05x SPI clk single bit

Question asked by oleon.alexandre on May 14, 2014
Latest reply on May 16, 2014 by oleon.alexandre
Hi,

I have a PCB with a STM32F051 connected to 3 ADCs (max11167) in daisy chain.
Page 29 Figure 14 of the datasheet shows the schematic I implemented and Page 21 shows how to configure the chips....

My problem is (page 21): "The load process is enabled on the falling edge of CNVST when SCLK is held high. "

The SPI is normally in Low Polarity and Falling Edge,

But in order to create the situation above I switch on the fly the polarity and Edge of the system to get the CLK high while CNVST falls... (I attached a screenshot...)
Very dirty way.. and I'm not sure if the ADCs are not upset by the extra clk falling edge at the end of the communication when I go back to the normal polarity.

void ADCs_init(void)
{
    uint16_t tmpreg = 0;
    SPI_Cmd(SPI1, DISABLE);    
    tmpreg = SPI1->CR1;
    tmpreg &= 0xFFFC;
    tmpreg |= (SPI_CPHA_1Edge | SPI_CPOL_High);
    SPI1->CR1 = tmpreg ;  /* Write to SPIx CR1 */
    GPIO_SetBits(ADC_CNVST_PORT,ADC_CNVST_PIN);
    SPI_Cmd(SPI1, ENABLE);
 
    GPIO_ResetBits(ADC_CNVST_PORT,ADC_CNVST_PIN);   /* Drop CNVST to enable the load process */
     
    Send_Receive_Byte(0xC0);    // Daisy Chain Mode with busy indicator, Reference mode 0, Normal mode.
    Send_Receive_Byte(0xC0);    // Daisy Chain Mode with busy indicator, Reference mode 0, Normal mode.
    Send_Receive_Byte(0xC0);    // Daisy Chain Mode with busy indicator, Reference mode 0, Normal mode.
     
    GPIO_SetBits(ADC_CNVST_PORT,ADC_CNVST_PIN);
     
    SPI_Cmd(SPI1, DISABLE);
    tmpreg = SPI1->CR1;
    tmpreg &= 0xFFFC;
    tmpreg |= (SPI_CPHA_2Edge | SPI_CPOL_Low); 
    SPI1->CR1 = tmpreg ;  /* Write to SPIx CR1 */
    SPI_Cmd(SPI1, ENABLE); 
 
}
uint8_t Send_Receive_Byte(uint8_t byte)
{
    /*!< Send byte through the SPI1 peripheral */
    SPI_SendData8(SPI1, byte);
    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET);
 
    /*!< Return the byte read from the SPI bus */
    return SPI_ReceiveData8(SPI1);
}

Do you know a nice way to control the CLK level?
 
Thanks,
Alex

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