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DMA and CPU accessing SRAM same time

Question asked by madhavan.niranjan on Mar 19, 2014
Latest reply on Mar 20, 2014 by madhavan.niranjan
I am working on a system using STM 32F107 processor(connectivity line). Because of our requirement same memory location of SRAM is accessed by both CPU and DMA. CPU is supposed to move the data from initial location A to location B(on SRAM) while DMA is supposed to update location A. But we are experiencing a duplicate data at location B. This can only happen if the DMA is not updating during CPU is moving data from A to B. What could be the reason for this? Is this due to a BUS crunch? When CPU and DMA is accessing same peripheral, DMA should get priority right? In that case we should not be getting duplicate data. Any inputs are appreciated.