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STM32F4 bxCAN FiFo Release Issues

Question asked by conner.gary on Mar 13, 2014
Latest reply on Mar 13, 2014 by Clive One
Can anyone tell me if the following is normal functionality of the RFR register:
Processor clock 168 MHz
APB1 bus 42 MHz
After reading the Receive FiFo and releasing by setting RFOM1 bit to 1 in the RF1R register, we must wait until the RFOM1 is reset to 0 by the hardware before exiting the interrupt.  If we exit the interrupt while RFOM1 bit is still set, the interrupt routine is immediately re-entered and the subsequent reading of the RIR register returns a value with eroneous values.

We never saw this issue using the an STM32F3 processor at 72 MHz and APB1 bus at 36 MHz.