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ST32F4 SPI recieve stream length 256 bits - how must they be framed

Question asked by Cliffy on Mar 6, 2014
Latest reply on Mar 7, 2014 by Cliffy
Hi all,

I'm trying to interface a multi-channel ADC to the F4 series over SPI or perhaps I2S.
Need to achieve DMA.

I have 256 bits. Can I use a NSS signal that is low for 256 serial clocks? Or do I need to burst both the NSS (CS) and SCLK signals so that the interface receives the data in 16-bit packets?

Regards,
M.

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