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Old DMA2 bug found in new MPU STM32F427 ?

Question asked by ludvik.zbynek.001 on Mar 4, 2014
Latest reply on Mar 5, 2014 by ludvik.zbynek.001


We use STM32Fxx MPU in many projects. During the development of new equipment with STM32F427, we have run into this problem:

We use SPI4, which is controlled by the DMA. Streamer DMA2_Stream1 is used for sending, DMA2_Stream0 for reading. DMA2_Stream0 generates an interrupt, which processes the data and restarts transmission (for many reasons it is not possible to use cyclic DMA).

Interrupt handler looks like this (actually the last version, program has been completely rewritten, unfortunately behavior is the same):

void DMA2_Stream0_Irq (){




   DMA_Cmd(DMA2_Stream0, DISABLE);

   DMA_Cmd(DMA2_Stream1, DISABLE); 

   while (DMA_GetCmdStatus(DMA2_Stream0)!=DISABLE) {}; 

   while (DMA_GetCmdStatus(DMA2_Stream1)!=DISABLE) {}; 

   DMA_SetCurrDataCounter(DMA2_Stream0, 14);

   DMA_SetCurrDataCounter(DMA2_Stream1, 14);

   DMA_MemoryTargetConfig(DMA2_Stream0, MemRx, DMA_Memory_0);

   DMA_MemoryTargetConfig(DMA2_Stream1, MemTx, DMA_Memory_0);

   DMA_Cmd(DMA2_Stream0, ENABLE);

   DMA_Cmd(DMA2_Stream1, ENABLE);


   SPI_Cmd(SPI4, ENABLE);  


Up to this point everything is ok. The transmission works perfectly, all tests of reliability and performance went well.

Then we implemented a simple DMA transfer memory2memory (for the purposes of TCP stack). We used DMA2_Stream7.

Separately, both communication works perfectly. If
, however, are used simultaneously, errors occur. DMA2_Stream0 interrupt is not called.

It looks as if the SPI4 read by one character less than sent. After error, DMA2_Stream0 is enabled (and waits indefinitely), has NDTR=1 and TCIF=0.  DMA2_Stream1 is stopped, has NDTR=0 and TCIF=1. From these data it is evident why SPI stops working.

I remembered that a similar errata was in the chip STM32F407. And indeed, error occurs only if source addr is FMC!!!

Shortly, if dma memory2memory is:

            SRAM->SRAM ... everything is ok

            SRAM->FMC ... everything is ok

            FMC ->FMC ... error

            FMC -> SRAM ... error

Oddly enough, this error is not described in the errata documentation. It is this error and is there a workaround ?

Or am I doing something wrong?