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Help with STM32F4 Clock config

Question asked by B3rsui on Feb 25, 2014
Latest reply on Feb 25, 2014 by B3rsui
Hi guys,

I need help to configure the stm32f4 clock to disable the pll and just work with the 8MHz external crystal of the discovery board.

The goal is to reduce as much as possible the consumption of the microcontroller and see which would be the best crystal/consumption relation to use in my project.

I generated a system_stm32f4xx with the Copia de STM32F4xx_Clock_Configuration_V1.1.0 but there wasn´t any difference in the consumption.

This is the result of the generated file:

* 5. This file configures the system clock as follows:
  *=============================================================================
  *=============================================================================
  *        Supported STM32F40xx/41xx/427x/437x devices
  *-----------------------------------------------------------------------------
  *        System Clock source                    | HSE
  *-----------------------------------------------------------------------------
  *        SYSCLK(Hz)                             | 8000000
  *-----------------------------------------------------------------------------
  *        HCLK(Hz)                               | 8000000
  *-----------------------------------------------------------------------------
  *        AHB Prescaler                          | 1
  *-----------------------------------------------------------------------------
  *        APB1 Prescaler                         | 1
  *-----------------------------------------------------------------------------
  *        APB2 Prescaler                         | 1
  *-----------------------------------------------------------------------------
  *        HSE Frequency(Hz)                      | 8000000
  *-----------------------------------------------------------------------------
  *        PLL_M                                  | 9
  *-----------------------------------------------------------------------------
  *        PLL_N                                  | 192
  *-----------------------------------------------------------------------------
  *        PLL_P                                  | 6
  *-----------------------------------------------------------------------------
  *        PLL_Q                                  | 4
  *-----------------------------------------------------------------------------
  *        PLLI2S_N                               | NA
  *-----------------------------------------------------------------------------
  *        PLLI2S_R                               | NA
  *-----------------------------------------------------------------------------
  *        I2S input clock                        | NA
  *-----------------------------------------------------------------------------
  *        VDD(V)                                 | 3.3
  *-----------------------------------------------------------------------------
  *        Main regulator output voltage          | Scale2 mode
  *-----------------------------------------------------------------------------
  *        Flash Latency(WS)                      | 0
  *-----------------------------------------------------------------------------
  *        Prefetch Buffer                        | OFF
  *-----------------------------------------------------------------------------
  *        Instruction cache                      | ON
  *-----------------------------------------------------------------------------
  *        Data cache                             | ON
  *-----------------------------------------------------------------------------
  *        Require 48MHz for USB OTG FS,          | Disabled
  *        SDIO and RNG clock                     |
  *-----------------------------------------------------------------------------

Any peace of advice will be appreciated.

Best regards,

Bruno

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