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SPI raise/fall time

Question asked by pacan.bogumil on Feb 10, 2014
Latest reply on Feb 13, 2014 by pacan.bogumil
I'm using STM32F373x SPI in slave mode. I get errors in about 0.1% bits transmitted, occurs in 50% of units from first production series of custom board. SPI lines have RC filter installed to improve EMC immunity. Rise/fall times are about 1us with filters and 10ns without them. I get no errors without filters. My question is what parameter do I exceeded?
Table 58 defines max. rise/fall 8ns (I guess only for master, cause load is also described). I think I'm not getting out of 30-70% duty cycle. Speed is 190kHz, reducing to 80kHz didn't changed anything.