I have a problem understanding the capture compare functionality.
I want to use channel1 to fire an interrupt if a match between CCR and counter is detected. In this case, CCR1 is set to 0xFFF+1. So the interrupt should never rise, because the counter restarts at 0xFFF this works fine for the TIM_OCMode_Toggle initialized on Channel3. Why is the TIM_IT_CC1 interrupt raised each counter overflow?
this guy describes how it works, but why do the interrupt rises when the pulse is higher than the counter counts?
Can someone help me understanding this?
By the way, I'm using an STM32F407.