AnsweredAssumed Answered

LIS3DH FIFO Int generation

Question asked by hadi.peyman on Jun 12, 2015
Latest reply on Nov 17, 2015 by ray.john.001
Hi all,

I am trying to use my LIS3DH in FIFO Stream mode.
I am trying to configure the accelerator to generate an interrupt whenever the FIFO is full.
However it never generates any interrupts.
I have configured the registers as following:
CTR_REG1= 0x57
CTR_REG2=0x00
CTR_REG3=0x02
CTR_REG4=0x08
CTR_REG5=0x48
FIFO_CTR_REG=80

I have noticed that when I read FIFO_SRC_REG for debugging the value is 0x20 which means that the FIFO is empty. Also when I read the value of FIFO_CTR_REG the value is 0x00!
any idea?

Regards,
Peyman

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