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ADC end of conversion

Question asked by be_senyor.ezra on Oct 26, 2010
Latest reply on Dec 28, 2010 by tardio.massimo
hi.
i cant understand why EOC wont go up to "1" after conversion. i can see the result in ADC->DR but the flag wont go up.
why?

thanks.


#include "stm32F10x.h"
#define CCR_ENABLE_Set          ((uint32_t)0x00000001)

void setsystemclock(void);

__IO uint16_t ADCConvertedValue;
int temp=0;
int main(void)
{


    setsystemclock(); //set system clock to 24Mhz3

    //rcc CONFIGURATION
   RCC->AHBENR=RCC_AHBENR_DMA1EN; //dma clock enable
   RCC->APB2ENR=RCC_APB2ENR_IOPCEN | RCC_APB2ENR_ADC1EN; //portc and ADC clock enable.

    //GPIO CONFIGURATION
   GPIOC->CRL=0x0;// ADC1_IN14


   //ADC configuration
   ADC1->CR1=ADC_CR1_SCAN;
   ADC1->CR2=ADC_CR2_ALIGN | ADC_CR2_EXTSEL;// |ADC_CR2_DMA ; //data align right , software start

   ADC1->SMPR1=0;// 1.5 cycles conversion time
   ADC1->SQR3=0xe;//channel number 14 PC4 first conversion


   //ADC1->CR2 |=ADC_CR1_SCAN  ;  /* Enable ADC1 DMA */
   ADC1->CR2 |=ADC_CR2_ADON; /* Enable ADC1 */

   ADC1->CR2 |=ADC_CR2_RSTCAL ;//reset calibration
   while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0x00); //wait for   end of ADC1 reset calibration register

   ADC1->CR2 |=ADC_CR2_CAL;/* Start ADC1 calibaration */

   while((ADC1->CR2 & ADC_CR2_CAL) != 0x00);/* Check the end of ADC1 calibration */

   ADC1->CR2 |=ADC_CR2_SWSTART |ADC_CR2_EXTTRIG; /* Start ADC1 Software Conversion */
    while(1)
    {
temp=ADC1->SR+1;

  if((temp&ADC_SR_EOC)>0)
  {

    temp=ADC1->DR;
    ADC1->CR2 |=ADC_CR2_SWSTART |ADC_CR2_EXTTRIG;

    temp=temp+1;

  }

    }

}
void setsystemclock(void)
{

      RCC->CR |= RCC_CR_HSEON;
    // Wait until it's ready
    while ((RCC->CR & RCC_CR_HSERDY) == 0)
        ;

    // Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)
    // for 8*3 = 24 MHz
    RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;

    // Start PLL
    RCC->CR |= RCC_CR_PLLON;
    // Wait until it's ready
    while ((RCC->CR & RCC_CR_PLLRDY) == 0)
        ;

    // Select PLL as system clock
    RCC->CFGR |= RCC_CFGR_SW_PLL;

    // Here we can check if PLL is used, and maybe disable HSI

    // Disable HSI
    RCC->CR &= ~RCC_CR_HSION;

    RCC->CFGR|=RCC_CFGR_MCO_2; //sys clock output
}



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