AnsweredAssumed Answered

Dead Time

Question asked by be_senyor.ezra on Oct 25, 2010
Latest reply on Oct 27, 2010 by brazov.ajeje
hi

i am trying to activte TIM1 in complementary mode with dead time.

but for some reason i get areverse dead time (both channels are at "1" instade of "0")
why is that i could not find such an option in the manual probebly missed something  but what?


thanks.

#include "stm32F10x.h"

void setsystemclock(void);



int main(void)
{

    setsystemclock(); //set system clock to 24Mhz

    //rcc configuration

    RCC->APB2ENR= RCC_APB2ENR_IOPBEN  |RCC_APB2ENR_IOPAEN | RCC_APB2ENR_TIM1EN |RCC_APB2ENR_AFIOEN  ;

    //GPIO configuration

 GPIOB->CRH=0xbb00000;//alternative function output up to 50mhz PB pins 0,1


GPIOA->CRH=0x0bb;//alternative function output up to 50mhz PB pins 0,1



    TIM1->ARR=1374; /* Set the Autoreload Register value (Count/f)=(1/(wanted freq))*/
    TIM1->EGR=TIM_EGR_UG;/*!<Update Generation */

    TIM1->CR2=TIM_CR2_OIS1  ; /*!<Output Idle state 2 (OC2 output) */
    TIM1->CCMR1=TIM_CCMR1_OC1M ;  /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
    TIM1->CCR1=480; /* Set the Capture Compare1 Register value (Duty Cycle)*/
    TIM1->CCER=TIM_CCER_CC1E |TIM_CCER_CC1NE | TIM_CCER_CC1P  | TIM_CCER_CC1NP ; /*!<Capture/Compare 1 output enable */

    TIM1->CCMR1|=TIM_CCMR1_OC1PE ; /*!<Output Compare 1 Preload enable */

    TIM1->CR1=TIM_CR1_ARPE; /*!<Auto-reload preload enable */

    TIM1->BDTR=TIM_BDTR_OSSR| TIM_BDTR_OSSI | TIM_BDTR_LOCK_0 | 2 | TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_AOE;
     TIM1->CR1=TIM_CR1_CEN;  /*!<Counter enable */
TIM1->BDTR=TIM_BDTR_MOE;

    while(1)
    {



    }

}
void setsystemclock(void)
{

      RCC->CR |= RCC_CR_HSEON;
    // Wait until it's ready
    while ((RCC->CR & RCC_CR_HSERDY) == 0)
        ;

    // Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)
    // for 8*3 = 24 MHz
    RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;

    // Start PLL
    RCC->CR |= RCC_CR_PLLON;
    // Wait until it's ready
    while ((RCC->CR & RCC_CR_PLLRDY) == 0)
        ;

    // Select PLL as system clock
    RCC->CFGR |= RCC_CFGR_SW_PLL;

    // Here we can check if PLL is used, and maybe disable HSI

    // Disable HSI
    RCC->CR &= ~RCC_CR_HSION;

    RCC->CFGR|=RCC_CFGR_MCO_2; //sys clock output
}


Outcomes