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STM32F3: timer synchronization ARR change

Question asked by pavlata.karel on Jan 24, 2014
Latest reply on Jan 29, 2014 by pavlata.karel

I'm using TIM1 and TIM8 of STM32F3 to generate PWM signals. I'm using both of the timers in combined PWM mode so that I can get high frequency/high resolution center aligned 4CH PWM. Moreover I'm synchronizing the timers so TIM1 is a master and slave timer (TIM8) enables(starts counting) exactly with TIM1. This works fine, the CCR registers are filled with the same values so the generated signals are in phase (very small delay between master and slave timers, which is acceptable). The problem rises when I try to update the period (ARR) of the timers on the fly. ARR being preloaded, I disable the update event, change the ARR registers and enable update event in the interrupt form CC1 of one of the timers (so the enable happens far from timer overflow). I'd expect the signals to be in phase after the change of the frequency, but (at least for me) surprisingly the generated signals phase changes (no change to CC regs.). The phase change does not occur all the time and correlates with the change of period - i.e. signals from one timer delays or overtakes the others when the change in period is positive or negative. Any thoughts on solution and how this is happening? The PWM frequency is around 100kHz and the write to ARR comes once a 100ms). thanks, karel