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STM32107 Default Clock configuration

Question asked by troncoso.orlando on Jan 19, 2014
Latest reply on Jan 19, 2014 by troncoso.orlando
I am trying to figure out the default clock speeds (after reset) for the buses and the peripherals and system clock for the STM32107VC. I am reading the STM32107 Reference Manual RM0008 on page 123.

One thing I do not understand is that the RCC_CFGR register reset value is 0x00000000. That register contains the PLLMUL field. Which is used to setup the clocks on page 123. When I look at the description of PLLMUL it says that the value 0x0 is reserved.

Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
000x: Reserved

How can this be? because the value of PLLMUL 0x000x at reset, I cannot figured out what PLLCLK is. Is this a typo or something?

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