I've got a SPI device that wants me to lower CS* then transfer data on the SPI pins, then raise CS*. (This is not an uncommon requirement :-) But I am really perplexed how this is supposed to be achieved. One way I've worked it is to write to the data register, then spin loop on the status register until RXNE is true (indicating that a full 8 (or 16) bits have been 'clocked in') and then raising CS. Waiting for BSY to go low exits to early and of course waiting for TXE to go true exits way early as that gets set right after the data is loaded into the shift register. It would be wonderful if there was something like the SDIO state machine we could use here. Is there a way to know the byte is transmitted *other* than watching RXNE?