AnsweredAssumed Answered

thakns JW, but it doesnt work

Question asked by guwono.septijo on Jan 6, 2014
From: waclawek.jan
Posted: Monday, January 06, 2014 1:34 PM
Subject: STM32F030F4P6 I2C Slave Transmitter Problem : TXI event triggered more times than requested by I2C master
RM0091, Rev4, 24.7.7 (I2Cx_ISR), Bit 1 TXIS: Transmit interrupt status (transmitters)
[...] Note: This bit is cleared by hardware when PE=0.

JW


thanks JW for your Reply, but it doesn't work :(

i try it with this :

I2C1->ISR &= (uint32_t)0xFFFFFFFD;

it is stated in RM0091 :

Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the I2Cx_TXDR register is empty and the data to be
transmitted must be written in the I2Cx_TXDR register. It is cleared when the next data to be
sent is written in the I2Cx_TXDR register.
This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1).
Note: This bit is cleared by hardware when PE=0.

i'm even try to add

I2C_StretchClockCmd(I2C1,DISABLE);

etc .. but still no luck.

others ? :).

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