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Monitoring VDD using the PVD feature

Question asked by grace.richard on Dec 18, 2013
Latest reply on Nov 24, 2014 by Tappenzee
I am using a STM32F203IGT6 trying to detect low VDD using the PVD feature.  This seems simple, but I cannot make it work.  My initialization code is below.  I start the peripheral clock set the PLS and PVDE bits (CS = 0x00F0), but the PVDO bit is the CSR does not change when I lower VDD from 3.3 to 2.5V.

The reference manual claims that the PVD monitors VDD/VDDA.  Do both of these voltages need to be blow the threshold?

    RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
    
    PWR->CR |= 0xe0;  //PV26;  // Set power voltage detection threshold 
    PWR->CR |= PVDE;  // Enable power voltage detection  





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