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Problems with the configuration of the Input Capture Filter

Question asked by short.simon on Dec 11, 2013
Latest reply on Dec 11, 2013 by Clive One
Hi community,
i've got a question dependig on the configuration of the input capture filter of the stm32f407.
I found the following lines in the datasheet (depending TIMx_CCMR1 register):

===============================================================
Bits 7:4IC1F: Input capture 1 filter
This bit-field defines the frequency used to sampleTI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8
Note: In current silicon revision, fDTSis replaced in the formula by CK_INT when ICxF[3:0]= 1, 2 or 3
===============================================================

My settings are:
f_clk_int = 84MHz, fDTS = 0.25*f_clk_int, maximum allowed input frequency = 5KHz

I want to configure the filter in that way, that a input signal must at least have a puls width of 100µs. If I have a sample frequency(fDTS) of 21MHz, I would need a filter counter value (N) of 2100. But, where can I set this counter value? I think my main problem is that I don't understand the datasheet in that case.

I would be happy if anyone could help me.

Simon


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