I have an interest in running Linux (uClinux) on the Cortex M4, namely one of the MCU’s in the STM32F4 series. These MCU’s have I-code/D-code caches for flash access as part of the ART accelerator, but clearly the internal flash is not nearly large enough to satisfy the requirements for uClinux; executing from external RAM is a must. However, I am a bit worried about the performance implications by doing so, since external RAM appears to be completely uncached.
However, external RAM can be remapped to the code space (< 0x20000000) and the RM0090 reference manual states that “In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance.” Does this means it allows for cached instruction fetches from the external RAM (through the I-code bus)? Or is it simply to prevent arbitration over the S-bus when e.g. using the internal SRAM at the same time? I guess the latter.