AnsweredAssumed Answered

stm32 I2s in slave mode Timing

Question asked by on Nov 22, 2013
The stm32 chip has a error for I2S in slave mode (stm32f40x Errata sheet 2.4.1).
2.4.1 In I2S slave mode, WS level must be set by the external master when enabling the I2S
In slave mode, the WS signal level is used only to start the communication. If the I2S (in slave mode) is enabled while the master is already sending the clock and the WS signal level is low (for I2S protocol) or is high (for the LSB or MSB-justified mode), the slave starts communicating data immediately. In this case, the master and slave will be desynchronized throughout the whole communication.
The I2S peripheral must be enabled when the external master sets the WS line at:
High level when the I2S protocol is selected
By the I2S format , I can see it's very easy:
1.SCLK is the bit clock.
2.WS is frame clock, low to start, left channel first and turn it high to right channel.
3.SD is the data stream, start by WS low delay 1 bit.

The errata sheet given workaround is too simple, has difficult to understand, using I2S slave mode what's its Timing? Has anyone can give me more details.
Thanks for your help.