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SPI DMA FIFO Error Issue (FEIFx)

Question asked by mapletron5000 on Oct 25, 2013
Latest reply on Apr 22, 2016 by Old Guy From Toon
I'm having a terrible time diagnosing this error on an F407IG chip.  I am trying to TX/RX SPI via DMA.  Currently I am getting good transactions, according to the external logic analyzer, from lengths of 1 to hundreds of bytes.  However, each and every time instead of getting a transfer complete interrupt, I get a FIFO error instead.  The data makes it through just fine, every last bit of it, but the error occurs somewhere during the stream and seemingly prevents the transfer complete interrupt from firing.

According to the reference manual, this error disables the dma stream (EN bits in the DMAx_SxCR register), however the remainder of my data goes through, as if the module was running normally.  I have tried running the bus at low speeds (~200khz) up to about 10mhz with identical results. I have tried different SPI / DMA channel combinations as well as various combinations of FIFO settings (and disabling the FIFO altogether).  Nothing else is running on the chip, so theoretically there shouldn't be any memory bus contention or DMA channel contention.

Any thoughts or directions to take this would be incredibly helpful.