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STM32F373 SDADC Gain Error Issue

Question asked by conner.gary on Oct 23, 2013
Latest reply on Nov 22, 2013 by Igor Cesko
Using the 3 channels of the SDADC in Single Ended Zero Reference Mode, Gain 1, with a SDREF at 2.5V.  Spec lists gain error of -2.4% to -3.1%, but our devices appear to have a positive gain error of approx +2.8%.  Offset calibration run and offset values in reg CONF0R approx 0x05e3.  Measured 1.8241V at ADC input, ADC value reads 0x4030.  Per the formula from AN4207, this is equivlent to 1.8768V.  According to AN4207, the definition of negative gain error would result in an ADC reading less than the measured value. 

Is this an known issue?  Is there any way to create this problem in software or extenal hardware?