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Peripheral to memory DMA places data at bottom of buffer

Question asked by viveros.solomon on Oct 21, 2013
Latest reply on Oct 22, 2013 by Clive One
I've DMA1 stream 3 channel 0 configured to handle the I2S2 data coming in from my UDA1380 codec and what I notice is that when configuring the Memory0BaseAddr to be the beginning of my circular buffer, the contents at the interrupt show the data being placed at the end of my buffer, moving toward the front[so in the case of four blocks, rather than placing the data at Block[0], I see the data being placed in Block[3], then decrementing to Block[2] the next interrupt]...I'm a little unclear as to what part of my code could be causing this...any insight would be much appreciated...

/* CODEC_I2S peripheral configuration */
 SPI_I2S_DeInit(SPI2);
 I2S_InitStructure.I2S_AudioFreq = AUDIO_FREQUENCY;
 I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
 I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
 I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;
   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
   I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
   I2S_Init(SPI2, &I2S_InitStructure);
   I2S_Cmd(SPI2, ENABLE);
    
   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
   DMA_Cmd(DMA1_Stream3, DISABLE);
   DMA_DeInit(DMA1_Stream3);
 
 DMA_InitStruct.DMA_Channel = DMA_Channel_0;
 DMA_InitStruct.DMA_PeripheralBaseAddr = (uint32_t)&(SPI2->DR);
 DMA_InitStruct.DMA_Memory0BaseAddr = (uint32_t)&Uda1380AdcAudio.Uda1380AdcBlock;
 DMA_InitStruct.DMA_DIR = DMA_DIR_PeripheralToMemory;        
 DMA_InitStruct.DMA_BufferSize = DMA_TRANSFER_BLOCK_SIZE * 2;      
 DMA_InitStruct.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
 DMA_InitStruct.DMA_MemoryInc = DMA_MemoryInc_Enable;      
 DMA_InitStruct.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
 DMA_InitStruct.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;  
 DMA_InitStruct.DMA_Mode = DMA_Mode_Normal;              
 DMA_InitStruct.DMA_Priority = DMA_Priority_High;        
 DMA_InitStruct.DMA_FIFOMode = DMA_FIFOMode_Disable;       
 DMA_InitStruct.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
 DMA_InitStruct.DMA_MemoryBurst = DMA_MemoryBurst_Single;     
 DMA_InitStruct.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
 while( DMA_GetCmdStatus( DMA1_Stream3 ) == ENABLE );
 DMA_Init( DMA1_Stream3, &DMA_InitStruct );
 DMA_ITConfig( DMA1_Stream3, DMA_IT_TC, ENABLE );
 DMA_Cmd( DMA1_Stream3, ENABLE );
    
 SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
 
 NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream3_IRQn;
 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
 NVIC_Init(&NVIC_InitStructure);

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