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STM32F0 Analog/Digital supply power up sequence, rise time rates?

Question asked by felder.norman on Oct 19, 2013
Latest reply on Oct 22, 2013 by felder.norman
I'm new to the ST product line.  While reading the datasheet for the STM32F051 I came across the following in section 3.5.1 "Power supply schemes":
The VDDA voltage must always be greater or equal to the VDD voltage level and must be provided first.

I haven't been able to determine what "first" means.  If VDD and VDDA are connected to the same 3.3V supply, so they both power up and down at the same time, is that good enough?  Do I need to do something to somehow enforce a VDDA-first sequence?  If that's the case, where is the necessary timing defined?

In section 6.3.2 "Operating conditions at power-up/power-down", Table 21 shows minimum VDD and VDDA fall times of 20 us/V.  Again, is this something I need to enforce?  Under normal circumstances the capacitors on the power rails would give plenty of fall time.  However, what happens if the 3.3V power supply is accidentally shorted resulting in a very rapid fall time?  Will the chip be damaged?

Thank you very much in advance.
Best regards,