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Understanding the purpose of ADC_SMPR

Question asked by xol.xol on Oct 13, 2013
Latest reply on Oct 14, 2013 by waclawek.jan
Hi,
I'm trying to understand what the ADC_SMPR register is used for.
According to Reference Manual we have following control on the ADC conversion time:

ADC_CR1 Register:
Bits 25:24 RES[1:0]: Resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit (15 ADCCLK cycles)
01: 10-bit (13 ADCCLK cycles)
10: 8-bit (11 ADCCLK cycles)
11: 6-bit (9 ADCCLK cycles)

But we still have ADC_SMPR 1/2:
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles

I understand that CR1 defines a minimal number of ADC clocks required for conversion while SMPR defines actual number of clocks that core will use. If my assumption is correct I want to understand how the extra clocks are used. Is it a simple delay and if yes is conversion done at the beginning or at the end of SMPR interval? If this time is used for better sampling or holding please tell us how and what is the precision improvement with a number of conversion clocks increase?

Thanks.
 

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