AnsweredAssumed Answered

Bad levels output on SDIO_CLK and PWM

Question asked by rocca.stephane on Oct 2, 2013
Latest reply on Oct 4, 2013 by rocca.stephane
Hi all,

I probably made a mistake in my first layout for STM32F103RE (LQFP64), with SDIO bus. My 400 KHz SDIO_CLK output is not consistent on oscillo : I see variations in the levels of the HIGH and LOW that vary with a fixed period :
- sometimes, HIGH+3.3 and LOW_0V are both correct,
- then HIGH level decrease, and LOW increase
- until HIGH and LOW levels are nearly the same at 1.6V

This variations are repeatable at a fixed period : approx 4 times the 400 KHz period.

The oscillations in levels are awefull when using HSE (8 MHz) as source for PLL at 72 MHZ, and are still visible, and probably a problem too, when HSI is used as a source for PLL at 64 MHz.
When using HSI, HSE is OFF : RCC_HSEConfig(RCC_HSE_OFF);

I tried to cut the line of the GND return path of the Crystal too : same result...

Problem is the same with a 400 KHz PWM with TIM5.

Bad layout I'm afraid of. I was thinking about bad decoupling perhaps ?

What I did for decoupling : 0.1uF CER on each VDD and VDDA, +4.7uF CER on VDD3 according to datasheet.
VBAT is at 3.3V, but without decoupling capacitor.

Do you see any error in my decoupling schem, anything I should work at ???

Thanks in advance for your help ;)