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OCREFCLR is not reset after update event

Question asked by frank bolatoli on Sep 24, 2013

I have a problem using the OCREFCLR input to TIM1 on a STM32F3.

I have set up TIM1: upcounting, CH1 in TIM_OCMode_Combined_PWM2 and CH2 in TIM_OCMode_PWM1. I have set OC1CE (Output Compare 1 Clear Enable) and OC2CE (Output Compare 2 Clear Enable) to 1.

The output from Comparator 1 is used as OCREFCLR input signal.

I can see that when the comparator output goes high for the first time, the PWM pulse is cleared as expected. But it seems like the PWM output is not reset at next update event. The comparator output goes low before the update event, so the OCREFCLR should not be active after the update event. After this the TIM PWM output is low forever.

Any ideas?

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