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UDIS/ URS - Bit, stm32F3

Question asked by stojanovski.martin on Sep 16, 2013
Latest reply on Sep 16, 2013 by stojanovski.martin
Hello my dear Forumers,


I'm having difficulties to understand the Update Disable bit and Update Request bit.

In the peripherial libs it is said, and i quote:

Configures the TIMx Update Request Interrupt source.
  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
  * @param  TIM_UpdateSource: specifies the Update source.
  *          This parameter can be one of the following values:
  *            @arg TIM_UpdateSource_Regular: Source of update is the counter
  *                 overflow/underflow or the setting of UG bit, or an update
  *                 generation through the slave mode controller.
  *            @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
  * @retval None
  */
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)



and if i set the UDIS bit it says that the Update Event is NOT generated by the timer itself ( counting overflow) but if i MANUALLY set the UG bit i will generate an interrupt?

Does this mean that whenever i set the UDIS bit

TIM_UpdateDisableConfig(TIM1,ENABLE);

and set the UG-BIT with  :

TIM1->EGR |= 1UL;

 an interrupt will be generated and the void TIM1_UP_TIM16_IRQHandler() will be called?

- Because the IRQ handler isnt executed when  active the UDIS-bit.

So to sum up. URS-setting : Only the timer itself( over/underflow ) can generate an interrupt
                      UDIS - setting : Only setting the UG-Bit can make an interrupt.

Thanks in advance, Martin

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