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ADC offset error

Question asked by rouse.alan.001 on Sep 6, 2013
Latest reply on Sep 7, 2013 by baird.hal.001
I am using 2 ADC inputs on an STM32F103.  Vref is 2.500V, from a voltage reference. One input is multiplexed via relays from a variety of external analogue signals and works well.  The other is used to monitor the supply voltage via a 68K/10K resistor divider, with a 100nF capacitor across the 10K.  The ADC should therefore give a reading of 0...4095 from a battery voltage in the range 0...19.5V.

I have measured the voltage on the ADC input pin and it is Vbatt/7.80 as expected.  The ADC reading varies linearly with the battery voltage, but has a fixed offset, regardless of battery voltage.  The offset varies between supposedly identical targets.  Three samples give offsets of  -43, +83 and -55, giving voltage reading errors of up to 0.4V.

I have checked to make sure that no I/O pins exceed the supply rails.  The strange thing is that the channel used to monitor the external analogue signals doesn't exhibit any significant offset.  That input goes to Vdd when no external signal is being sampled,but I have tried forcing it to Vss and that makes no difference.

After each power-up the firmware does an ADC calibration (although I can't believe that any initial calibration errors would be of the magnitude I am seeing).

Any ideas?