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Question asked by loeffel.raphael on Aug 26, 2013
Latest reply on Aug 28, 2013 by loeffel.raphael

I tried to migrate a working SPI master from a STMF20x device to the STM32F37x device. The SPI master should write and read 8bit data to some SPI memory devices (EEPROM or flash) by using DMA. Attached is the actual source code.

It seems that I now run into troubles with the new FIFO feature at the SPI periphery of the STM32F37x. Transmitting of the data works fine but receiving don't. It seems that the first three read bytes are wrong followed by the expected bytes. E.g. if I want to read 4 bytes from the serial memory the first 3 bytes are void and the 4. bytes contains the expected data of the first received byte. Both the SPI and the DMA are configured for 8bit word length. Also the RX FIFO level is set to 1/4. Therefore the automated data packing shouldn't be a problem. The DMA will also got the expected amount of requests. From my point of view it seems that the FIFO access doesn't work with 8bit data length and DMA access. For testing I tried to read the data by polling the RXNE flag instead of using the RX DMA (See define"BASESPI_DMA_RECEIVE"). This approach seems to work. Any ideas how I will get the RX DMA working and how I have to configure the SPI FIFO? Is there a possibility to disable the SPI FIFO?

Best regards Raphael