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STM32F405 ETH pkt receive but not transmit

Question asked by goncharov.sergey on Aug 8, 2013
Latest reply on Dec 16, 2014 by Smart65
MCU: STM32F405RG
PHY: DP83848I
CRYSTAL: 25MHz on both devices
I've managed to succesfully receive packages, atleast i see packets fully conform ARP request that sent from PC, but when i'm trying to compose ARP request and send it from MCU... i'm sending every second, i see blinking Act led on the PHY as my test LED on MCU blinks, but wireshark does not show any packets sent by MCU and received by pc. i've tryed both stm32fxx7_eth lib and stm32_lib, as i understand they are differs mostly in section relative to enhanced descriptor registers plus some more TypeDefs for convinience and Rx/TxDesc and buffers declared in lib, no need to declare it in custom driver, all main functions  in both libs are the same. Phy normally starts, i can read and write to its' registers, link is stable, I've connected PHY to switch using regular LAN cable and connected to the very same switch the PC, i've tryed to connect PC straight to the PHY with the same result - transmission does not work, but i can receive packets on the MCU side.My current code is:

/* Includes ------------------------------------------------------------------*/
#include "main.h"
 
 
//---------- Defines -----------------------------------------------------------
#define SYSTEMTICK_PERIOD_MS  10
 
#define DP83848_PHY
#define PHY_ADDRESS       0x01
 
#define ETH_RXBUFNB        8
#define ETH_TXBUFNB        2
 
//---------- Macros ------------------------------------------------------------
//---------- TypeDefs ----------------------------------------------------------
//---------- Variables ---------------------------------------------------------
ETH_InitTypeDef ETH_InitStructure;
/* Ethernet Rx & Tx DMA Descriptors */
ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
/* Ethernet buffers */
u8 Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
 
/* Global pointers to track current transmit and receive descriptors */
extern ETH_DMADESCTypeDef  *DMATxDescToSet;
extern ETH_DMADESCTypeDef  *DMARxDescToGet;
 
ErrorStatus HSEStartUpStatus;
vu32 Value = 0;
 
__IO uint32_t LocalTime = 0; /* this variable is used to create a time reference incremented by 10ms */
uint32_t timingdelay;
 
//$TOOLKIT_DIR$\config\linker\ST\stm32f405xG.icf
//==============================================================================
void main()
//==============================================================================
{
    /* Setup the MCU system. Initialize the Embedded Flash Interface, 
    initialize the PLL and update the SystemFrequency variable. */
    SystemInit();
    //----- LED ----------------------------------------------------------------
    GPIO_InitTypeDef GPIO_InitStructure;
    RCC_AHB1PeriphClockCmd(LED_GPIO_CLK, ENABLE);
    GPIO_InitStructure.GPIO_Pin =  LED_PIN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
    GPIO_Init(LED_PORT, &GPIO_InitStructure);
    GPIO_SetBits(LED_PORT, LED_PIN);
    GPIO_ResetBits(LED_PORT, LED_PIN);     
    //----- Init UART ----------------------------------------------------------
    UART_Init();
    if ((RCC->CR & RCC_CR_HSERDY) != RESET) printf(" HSE Is OK\r\n");
    PrintClock();
    //----- Init ETH -----------------------------------------------------------
    ETH_Conf();
    uint16_t reg = ETH_ReadPHYRegister(0x0001, PHY_ID_DR0);
    if (reg != 0) printf("ID0:0x%X\r\n", reg);
    reg = ETH_ReadPHYRegister(0x0001, PHY_ID_DR1);
    if (reg != 0) printf("ID1:0x%X\r\n", reg);
 
 
    printf("Starting Main Loop\r\n");
    while(1)
    {
        transmit_tPkt();
        //receive_Pkt();
        GPIO_WriteBit(LED_PORT, LED_PIN, Bit_SET);
        Delay(500);
        GPIO_WriteBit(LED_PORT, LED_PIN, Bit_RESET);
        Delay(500);
    }          
 
}
 
//==============================================================================
void PrintClock(void)
//==============================================================================
{
  RCC_ClocksTypeDef  rcc_clocks;
  uint32_t hclk = 0;
  /* Get hclk frequency value */
  RCC_GetClocksFreq(&rcc_clocks);
  hclk = rcc_clocks.HCLK_Frequency;
  printf("HCLK:%u\r\n", hclk);
}
 
 
//waits nCounts of 10mS
//==============================================================================
void Delay(uint32_t nCount)
//==============================================================================
{
  /* Capture the current local time */
  timingdelay = LocalTime + nCount; 
  /* wait until the desired delay finish */ 
  while(timingdelay > LocalTime)
  {    
  }
}
 
//==============================================================================
void Time_Update(void)
//==============================================================================
{
  LocalTime += SYSTEMTICK_PERIOD_MS;
}
 
//==============================================================================
void ETH_Conf(void)
//==============================================================================
{
    /* Enable SYSCFG clock */
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);     
    //Select MII interface (must be done before ETH clock enabled or while ETH under reset)
    SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
    /* Get HSE clock = 25MHz on PA8 pin(MCO) */
    //RCC_MCOConfig(RCC_MCO_HSE);
    RCC_ClocksTypeDef RCC_Clocks;
    /* Configure Systick clock source as HCLK */
    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
    /* SystTick configuration: an interrupt every 10ms */
    RCC_GetClocksFreq(&RCC_Clocks);
    SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
     
    /* Enable ETHERNET clock  */
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
                        RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
    //----------------------------
    GPIO_InitTypeDef GPIO_InitStructure;
    /* Enable GPIO clocks */
    RCC_AHB1PeriphClockCmd(PHY_CLK_GPIO_CLK | MDC_GPIO_CLK | MDIO_GPIO_CLK |
                            TXD0_GPIO_CLK | TXD1_GPIO_CLK | TXD2_GPIO_CLK |
                            TXD3_GPIO_CLK |TX_EN_GPIO_CLK |TX_CLK_GPIO_CLK |
                            CRS_GPIO_CLK | COL_GPIO_CLK | RXD0_GPIO_CLK |
                            RXD1_GPIO_CLK | RXD2_GPIO_CLK | RXD3_GPIO_CLK |
                            RX_CLK_GPIO_CLK | RX_DV_GPIO_CLK | RX_ER_GPIO_CLK
                            , ENABLE);
     
    //Configure GPIOs for ETH AF11 ---------------------------------------------
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;//GPIO_PuPd_UP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    //PHY_CLK
    GPIO_InitStructure.GPIO_Pin = PHY_CLK_PIN;
    GPIO_Init(PHY_CLK_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(PHY_CLK_GPIO_PORT, PHY_CLK_SOURCE, GPIO_AF_ETH);
    //MDIO
    GPIO_InitStructure.GPIO_Pin = MDIO_PIN;
    GPIO_Init(MDIO_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(MDIO_GPIO_PORT, MDIO_SOURCE, GPIO_AF_ETH);
    //MDC
    GPIO_InitStructure.GPIO_Pin = MDC_PIN;
    GPIO_Init(MDC_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(MDC_GPIO_PORT, MDC_SOURCE, GPIO_AF_ETH);  
    //TXD0
    GPIO_InitStructure.GPIO_Pin = TXD0_PIN;
    GPIO_Init(TXD0_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TXD0_GPIO_PORT, TXD0_SOURCE, GPIO_AF_ETH);
    //TXD1
    GPIO_InitStructure.GPIO_Pin = TXD1_PIN;
    GPIO_Init(TXD1_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TXD1_GPIO_PORT, TXD1_SOURCE, GPIO_AF_ETH);
    //TXD2
    GPIO_InitStructure.GPIO_Pin = TXD2_PIN;
    GPIO_Init(TXD2_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TXD2_GPIO_PORT, TXD2_SOURCE, GPIO_AF_ETH);
    //TXD3
    GPIO_InitStructure.GPIO_Pin = TXD3_PIN;
    GPIO_Init(TXD3_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TXD3_GPIO_PORT, TXD3_SOURCE, GPIO_AF_ETH);
    //TX_EN
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_Pin = TX_EN_PIN;
    GPIO_Init(TX_EN_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TX_EN_GPIO_PORT, TX_EN_SOURCE, GPIO_AF_ETH);
    //TX_CLK
    GPIO_InitStructure.GPIO_Pin = TX_CLK_PIN;
    GPIO_Init(TX_CLK_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(TX_CLK_GPIO_PORT, TX_CLK_SOURCE, GPIO_AF_ETH);
    //CRS
    GPIO_InitStructure.GPIO_Pin = CRS_PIN;
    GPIO_Init(CRS_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(CRS_GPIO_PORT, CRS_SOURCE, GPIO_AF_ETH);
    //COL
    GPIO_InitStructure.GPIO_Pin = COL_PIN;
    GPIO_Init(COL_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(COL_GPIO_PORT, COL_SOURCE, GPIO_AF_ETH);
    //RXD0
    GPIO_InitStructure.GPIO_Pin = RXD0_PIN;
    GPIO_Init(RXD0_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RXD0_GPIO_PORT, RXD0_SOURCE, GPIO_AF_ETH);
    //RXD1
    GPIO_InitStructure.GPIO_Pin = RXD1_PIN;
    GPIO_Init(RXD1_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RXD1_GPIO_PORT, RXD1_SOURCE, GPIO_AF_ETH);
    //RXD2
    GPIO_InitStructure.GPIO_Pin = RXD2_PIN;
    GPIO_Init(RXD2_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RXD2_GPIO_PORT, RXD2_SOURCE, GPIO_AF_ETH);
    //RXD3
    GPIO_InitStructure.GPIO_Pin = RXD3_PIN;
    GPIO_Init(RXD3_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RXD3_GPIO_PORT, RXD3_SOURCE, GPIO_AF_ETH);
    //RX_CLK
    GPIO_InitStructure.GPIO_Pin = RX_CLK_PIN;
    GPIO_Init(RX_CLK_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RX_CLK_GPIO_PORT, RX_CLK_SOURCE, GPIO_AF_ETH);
    //RX_DV
    GPIO_InitStructure.GPIO_Pin = RX_DV_PIN;
    GPIO_Init(RX_DV_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RX_DV_GPIO_PORT, RX_DV_SOURCE, GPIO_AF_ETH);
    //RX_ER
    GPIO_InitStructure.GPIO_Pin = RX_ER_PIN;
    GPIO_Init(RX_ER_GPIO_PORT, &GPIO_InitStructure);
    GPIO_PinAFConfig(RX_ER_GPIO_PORT, RX_ER_SOURCE, GPIO_AF_ETH);
  
   
   
  //--------------------------------
  /* Reset ETHERNET on AHB Bus */
  ETH_DeInit();
   
  /* Software reset */
  ETH_SoftwareReset();
   
  /* Wait for software reset */
  while(ETH_GetSoftwareResetStatus()==SET);
 
  /* ETHERNET Configuration ------------------------------------------------------*/
  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
  ETH_StructInit(Ð_InitStructure);
   
  /* Fill ETH_InitStructure parametrs */
  /*------------------------   MAC   -----------------------------------*/
  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable  ; 
  //ETH_InitStructure.ETH_Speed = ETH_Speed_100M;                                     
  ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;             
  //ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;                                                                                 
  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;                                                                                 
  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                                                                                                                                       
  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;                                                                                                      
  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;     
  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                            
  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;     
  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;                       
  /* Configure ETHERNET */
  Value = ETH_Init(Ð_InitStructure, PHY_ADDRESS);
 
    uint8_t hwaddr[6];
    hwaddr[0] =  MAC_ADDR0;
    hwaddr[1] =  MAC_ADDR1;
    hwaddr[2] =  MAC_ADDR2;
    hwaddr[3] =  MAC_ADDR3;
    hwaddr[4] =  MAC_ADDR4;
    hwaddr[5] =  MAC_ADDR5;
    /* initialize MAC address in ethernet MAC */
    ETH_MACAddressConfig(ETH_MAC_Address0, hwaddr);
   
  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
 
    /* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
    for(int i=0; i<ETH_TXBUFNB; i++)
    {
        ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
        //ETH_SetDMATxDescOwnBit(&DMATxDscrTab[i]);
    }      
  DMARxDscrTab->Status = ETH_DMARxDesc_OWN;
  /* Enable MAC and DMA transmission and reception */
  ETH_Start(); 
     
     
}
 
//==============================================================================
void NVIC_Configuration(void)
//==============================================================================
{
  NVIC_InitTypeDef   NVIC_InitStructure;
 
  /* Set the Vector Table base location at 0x08000000 */
  NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
 
  /* 2 bit for pre-emption priority, 2 bits for subpriority */
  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
   
  /* Enable the Ethernet global Interrupt */
  NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);   
   
}
 
 
 
 
// fill buf with servver_ip,macaddrmipaddr and arp related data, return packet size
//(*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
//==============================================================================
uint8_t Make_ARP_Request(uint8_t *server_ip, uint8_t *macaddr, uint8_t *ipaddr)
//==============================================================================
{
    uint8_t i=0;
    // dst and src addr 0-5, 6-11
    while(i<6)
    {
        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ETH_DST_MAC +i))=0xff;
        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ETH_SRC_MAC +i))=(*(macaddr + i));
        i++;
    }
    //frame type 2b (for ethernet 0x0806) 12-13
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ETH_TYPE_H_P )) = ETHTYPE_ARP_H_V; //0x08
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ETH_TYPE_L_P )) = ETHTYPE_ARP_L_V; //0x06
    // generate arp packet (op 2b) 0x01 for request(our case), 0x02 for response pos=>20-21
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_OPCODE_H_P))=ARP_OPCODE_REQUEST_H_V; //20th
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_OPCODE_L_P))=ARP_OPCODE_REQUEST_L_V; //21th
    // fill in arp request packet
    // setup hardware type to ethernet 0x0001 pos=>14-15
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_HARDWARE_TYPE_H_P )) = ARP_HARDWARE_TYPE_H_V;
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_HARDWARE_TYPE_L_P )) = ARP_HARDWARE_TYPE_L_V;
    // setup protocol type to ip 0x0800 pos=>16-17
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_PROTOCOL_H_P )) = ARP_PROTOCOL_H_V;
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_PROTOCOL_L_P )) = ARP_PROTOCOL_L_V;
    // setup hardware length to 0x06 pos=>18
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_HARDWARE_SIZE_P )) = ARP_HARDWARE_SIZE_V;
    // setup protocol length to 0x04 pos=>19
    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_PROTOCOL_SIZE_P )) = ARP_PROTOCOL_SIZE_V;
    // setup arp destination and source mac address
    for ( i=0; i<6; i++)
    {
        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_DST_MAC_P + i )) = 0x00; // pos=>32-37
        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_SRC_MAC_P + i )) = (*(macaddr + i));//pos=>22-27
    }
    // setup arp destination and source ip address
    for ( i=0; i<4; i++)
    {
         (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_DST_IP_P + i )) = (*(server_ip + i));//38-41
        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + ARP_SRC_IP_P + i )) = (*(ipaddr + i));//pos=>28-31
    }
    return 42;
}
 
 
//==============================================================================
void transmit_tPkt(void)
//==============================================================================
{
    uint32_t timeout = 0;
    /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
    if ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) == (u32)RESET)
    {
        printf("Tx start\r\n");
        //phy mac addr 
        uint8_t hwaddr[6];
        hwaddr[0] =  MAC_ADDR0;
        hwaddr[1] =  MAC_ADDR1;
        hwaddr[2] =  MAC_ADDR2;
        hwaddr[3] =  MAC_ADDR3;
        hwaddr[4] =  MAC_ADDR4;
        hwaddr[5] =  MAC_ADDR5;    
        //my ip addr
        uint8_t ipaddr[4];
        ipaddr[0] = 192;
        ipaddr[1] = 168;
        ipaddr[2] = 1;
        ipaddr[3] = 128;
        //srv ip addr
        uint8_t srv_ipaddr[4];
        srv_ipaddr[0] = 192;
        srv_ipaddr[1] = 168;
        srv_ipaddr[2] = 1;
        srv_ipaddr[3] = 1;         
        uint8_t len = Make_ARP_Request(srv_ipaddr, hwaddr, ipaddr);
        ETH_DMATxDescShortFramePaddingCmd(DMATxDescToSet, ENABLE);
         
        /* Setting the Frame Length: bits[12:0] */
        DMATxDescToSet->ControlBufferSize = (len & (uint32_t)0x1FFF);
        /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */   
        DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
        DMATxDescToSet->Status  &= ~(ETH_DMATxDesc_DP); // Enable Padding ( add padding for frame shorter than 64 bytes)
        DMATxDescToSet->Status  &= ~(ETH_DMATxDesc_DC); // Enable CRC
        /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
        DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
        /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
        if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
        {
            /* Clear TBUS ETHERNET DMA flag */
            ETH->DMASR = ETH_DMASR_TBUS;
            /* Resume DMA transmission*/
            ETH->DMATPDR = 0;
        }
        /* Wait for ETH_DMATxDesc_TTSS flag to be set */
        do
        {
            timeout++;
        } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
        /* Return ERROR in case of timeout */
        if(timeout == PHY_READ_TO)
        {
            printf("SEND TIMEOUT\r\n");
            return;
        }
        /* Clear the DMATxDescToSet status register TTSS flag */
        DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
         
        if (DMATxDescToSet->Status & ETH_DMATxDesc_IHE) printf("IPv4 Header Error \r\n"); // ipv4 header error
         
        /* Update the ENET DMA current descriptor */
        DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
    }
    else
    {
        printf("DMATxDscr Status is OWN\r\n");
    }
 
}
 
 
//==============================================================================
void receive_Pkt(void)
//==============================================================================
{
    //poll receive descriptors, will be cleared automatically
    ETH->DMARPDR = 1;
    ETH_DMAReceptionCmd(DISABLE);
    ETH_DMADESCTypeDef *DMARxDesc = DMARxDescToGet;
    //int i;
    //for(i=0; i < ETH_RXBUFNB; i++)
    //{
        /* Get the pointer on the ith member of the Rx Desc list */
        //DMARxDesc = DMARxDscrTab + i;
        /* Set Own bit of the Rx descriptor Status */
        if (DMARxDesc->Status != ETH_DMARxDesc_OWN)
        {
            uint8_t hwaddr[6];
            hwaddr[0] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 0));
            hwaddr[1] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 1));
            hwaddr[2] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 2));
            hwaddr[3] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 3));
            hwaddr[4] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 4));
            hwaddr[5] =  (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + 5));
            printf("DST MAC: %X %X %X %X %X %X \r\n", hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]);       
            if (((hwaddr[4] == MAC_ADDR4) && (hwaddr[5] == MAC_ADDR5)) || ((hwaddr[4] == 0xff) && (hwaddr[5] == 0xff)))
            {
                uint32_t framelength = ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> 16) - 4;
                printf("----------------------------------\r\n");
                for(uint32_t i = 0; i < framelength; i ++)
                    printf("%X ", (*(__IO uint8_t *)((DMARxDesc->Buffer1Addr) + i)) );
                printf("----------------------------------\r\n");
            }
            /* When Rx Buffer unavailable flag is set: clear it and resume reception */
            if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
            {
                /* Clear RBUS ETHERNET DMA flag */
                ETH->DMASR = ETH_DMASR_RBUS;
                /* Resume DMA reception */
                ETH->DMARPDR = 0;
            }
            DMARxDesc->Status = ETH_DMATxDesc_OWN;
        }
        /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
        /* Chained Mode */
        if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
        {
            /* Selects the next DMA Rx descriptor list for next buffer read */
            DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
            if(DMARxDescToGet->Status != 0)
            {
                DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Status);
            }
            else
            {
                DMARxDescToGet++;
            }
        }
        else /* Ring Mode */
        {
            if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
            {
                /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
                DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
            }
            else
            {
                /* Selects the next DMA Rx descriptor list for next buffer to read */
                DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));     
            }
        }      
         
    //}
    ETH_DMAReceptionCmd(ENABLE);
}


Sorry for the messy and amateur code, but it's just to test and learn how it all works. Thanx for any help.

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