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Input pull-up to pull-down duration on STM32F303

Question asked by Moore.Patrick on Jun 6, 2013
Latest reply on Jun 6, 2013 by Clive One
How long does it takes the STM32F303 to change an input from pull-up enabled to pull-down enabled? 

How long does it take to change an input from pull-up enabled to pull-down enabled?

It seems that if I read the input directly or shortly after changing the GPIO pull configuration, the input state is not stable...but I see the input line toggling between VDD and VSS on the scope (unless I pull it up or down externally with a few K ohms or less to VDD or VSS).

In this case the F303 is running at the maximum core and peripheral clock rates specified in the Rev 5 datasheet.  The clock source a very stable 8MHz TTL clock via the HSE input.

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