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Timer overflow when in PWM mode?

Question asked by nohaj.miroslav on May 20, 2013
Latest reply on May 22, 2013 by nohaj.miroslav

I'm running my code on STM32F103 chip, I've set up a PWM output from timer1 with period of 200 ms, pulse width 5 ms, it's working and can be seen with a scope on GPIOA_8. The thing is, that I want to do something when the timer overflows, on each overflow I toggled GPIOA_10, like this:

     while(1) {
          WORD val = TIM1->SR;
          if((val & 0x0001) == 0) {               // no overflow? continue
          TIM1->SR = val & 0xfffe;               // clear UIF flag
          if(GPIOA->ODR & (1 << 10)) {
               GPIOA->BSRR = (1 << 26);
          } else {
               GPIOA->BSRR = (1 << 10);

The problem is that even though I see the GPIOA_8 do the PWM output nicely, I can see the UIF to be set only like once in 10 secods (that would be like 500 PWM cycles). First I thought that I'm missing the UIF flag somehow (is it reset back to 0 in PWM mode by HW?), so I did the same with the interrupt, and even the interrupt gets called only like once in 10 secods (can see it on scope on the 2nd channel, or even by watching the debugger stop at breakpoint). 

I've went through the forum and found out that I shouldn't use RMW to clear UIF flag, I can test that in the evening (don't have the hardware with me right now), but I guess that won't help too much. UDIS in the TIMx_CR1 register is 0 so the UIF should be generated. 

What am I missing? Does this behave differently when the timer is in PWM mode?