AnsweredAssumed Answered

problem with B DMA2_Stream0_IRQHandler

Question asked by kakou.maroucha on May 3, 2013
Latest reply on May 4, 2013 by Clive One
Hello ,
I still novice in embedded programming and when i use DMA transfer between memories the program is blocked on "B DMA2_Stream0_IRQHandler" in the file startup_stm32f4xx.s
please it's urgent i need help !!
this is my code :


while(1)
{
 USART_ClearFlag(USART2,  USART_FLAG_TXE);
  USART_ClearFlag(USART2, USART_FLAG_RXNE);
if (USART_GetFlagStatus(USART2, USART_FLAG_TXE) != RESET)
    USART_SendData(USART2, Txvalue);
  if (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) != RESET)
    RxValue = USART_ReceiveData(USART2);
     tab_src[0]=RxValue;  // tab_src[0] contains the data to be transferd to flash memory via                                                  // DMA
      EXTI_GenerateSWInterrupt(EXTI_Line0);  //ISR generated when i press button to send                                                                               // data to flash memory 
       EXTILine0_Config();  
       }

void DMA_Config(void)
{
  NVIC_InitTypeDef NVIC_InitStructure;
  DMA_InitTypeDef  DMA_InitStructure;
  __IO uint32_t    Timeout = TIMEOUT_MAX;


  /* Enable DMA clock */
  RCC_AHB1PeriphClockCmd(DMA_STREAM_CLOCK, ENABLE);


  /* Reset DMA Stream registers (for debug purpose) */
  DMA_DeInit(DMA_STREAM);


  /* Check if the DMA Stream is disabled before enabling it.
     Note that this step is useful when the same Stream is used multiple times:
     enabled, then disabled then re-enabled... In this case, the DMA Stream disable
     will be effective only at the end of the ongoing data transfer and it will
     not be possible to re-configure it before making sure that the Enable bit
     has been cleared by hardware. If the Stream is used only once, this step might
     be bypassed. */
  while (DMA_GetCmdStatus(DMA_STREAM) != DISABLE)
  {
  }


  /* Configure DMA Stream */
  DMA_InitStructure.DMA_Channel = DMA_CHANNEL;
  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)tab_src;
  DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)tab_dst;
  DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory;
  DMA_InitStructure.DMA_BufferSize = (uint32_t)BUFFER_SIZE;
  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
  DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
  DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
  DMA_Init(DMA_STREAM, &DMA_InitStructure);


  /* Enable DMA Stream Transfer Complete interrupt */
  DMA_ITConfig(DMA_STREAM, DMA_IT_TC, ENABLE);


  /* DMA Stream enable */
  DMA_Cmd(DMA_STREAM, ENABLE);
 


  /* Check if the DMA Stream has been effectively enabled.
     The DMA Stream Enable bit is cleared immediately by hardware if there is an
     error in the configuration parameters and the transfer is no started (ie. when
     wrong FIFO threshold is configured ...) */
  Timeout = TIMEOUT_MAX;
  while ((DMA_GetCmdStatus(DMA_STREAM) != ENABLE) && (Timeout-- > 0))
  {
  }


  /* Check if a timeout condition occurred */
  if (Timeout == 0)
  {
    /* Manage the error: to simplify the code enter an infinite loop */
    while (1)
    {
    }
  }


void EXTI0_IRQHandler(void)
{


  if(EXTI_GetITStatus(EXTI_Line0) != RESET)
  {
   
         DMA_Config();
          EXTI_ClearITPendingBit(EXTI_Line0);
        
  }
}



   //Enable the DMA Stream IRQ Channel 
  NVIC_InitStructure.NVIC_IRQChannel = DMA_STREAM_IRQ;
  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  NVIC_Init(&NVIC_InitStructure);
}
thank you 





}

 

Outcomes