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External SRAM + USART Interrupt IO = USART RX Overrun?

Question asked by Mike on May 2, 2013
Latest reply on May 3, 2013 by Mike
I have the following configuration:
- 2 external SRAM chips (at 0x6000000 & 0x64000000)
- USART1 running in Interrupt IO mode.
- Stack in CCM

The SRAM and USART code is almost verbatim from the STM32F4 peripheral library examples.

Both SRAM chips work great.  The USART works great.  However, when I'm receiving a lot of data on the USART (approx 1024 bytes @ 115200 baud), and simultaneously reading and writing heavily to the external SRAM (a few hundred kilobytes at a time), the USART starts to get RX buffer overrun errors, and the data received is less than accurate. 

If I increase the addressSetupTime and dataSetupTime of the SRAM, the RX buffer overruns occur more frequently.  If I decrease these settings, I get fewer RX buffer overruns.  However, if I decrease them too much, the SRAM doesn't work.    Decreasing the amount of reads/writes per second to external SRAM also decreases/eliminates the occurrence of the RX buffer overruns.

It's as if the heaving reading and writing to SRAM causes resource contention for the MCU, and the USART RX interrupt can't be serviced in time.  I've tried setting the USART interrupt priority to the highest possible, but the problem remains the same.

Can anyone take a guess as to what might be causing this behavior?